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cy7c009v 3.3 v 128 k 8 dual-port static ram cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 38-06044 rev. *g revised november 18, 2013 3.3 v 128 k 8 dual-port static ram features true dual-ported memory cells which allow simultaneous access of the same memory location 128 k 8 organization (cy7c009) 0.35-micron cmos for optimum speed/power high-speed access: 15/20/25 ns low operating power ? active: i cc = 115 ma (typical) ? standby: i sb3 = 10 ? a (typical) fully asynchronous operation automatic power-down expandable data bus to 16 bits or more using master/slave chip select when using more than one device on-chip arbitration logic semaphores included to permit software handshaking between ports int flag for port-to- port communication dual chip enables pin select for master or slave commercial and industrial temperature ranges available in 100-pin tqfp pb-free packages available i/o control address decode a 0l ?a 16l ce l oe l r/w l busy l i/o control interrupt semaphore arbitration sem l int l m/s logic block diagram a 0l ?a 16l true dual-ported ram array a 0r ?a 16r ce r oe r r/w r busy r sem r int r address decode a 0r ?a 16r [1] [1] r/w l ce 0l ce 1l oe l i/o 0l ?i/o 8l ce l r/w r ce 0r ce 1r oe r i/o 0r ?i/o 8r ce r 17 8 17 8 17 17 note 1. busy is an output in master mode and an input in slave mode. cy7c008v cy7c018v cy7c009v cy7c019v 3.3 v 128 k 8 dual-port static ram
cy7c009v document number: 38-06044 rev. *g page 2 of 23 functional description the cy7c009v is a low-power cmos 64 k, 128 k 8 dual-port static ram. various arbitration schemes are included on the devices to handle situations when multiple processors access the same piece of data. two ports are provided permitting independent, asynchronous access for reads and writes to any location in memory. the devices can be utilized as standalone 8/9-bit dual-port static rams or multiple devices can be combined in order to function as a 16/18-bit or wider master/slave dual-port static ram. an m/s pin is provided for implementing 16/18-bit or wider me mory applications without the need for separate master and slave devices or additional discrete logic. application areas include interprocessor/multiprocessor des igns, communications status buffering, and dual-port video/graphics memory. each port has independent control pins: chip enable (ce ), read or write enable (r/w ), and output enable (oe ). two flags are provided on each port (busy and int ). busy signals that the port is trying to access the same location currently being accessed by the other port. the interrupt flag (int ) permits communication between ports or systems by means of a mail box. the semaphores are used to pass a flag, or token, from one port to the other to indicate that a shared resource is in use. the semaphore logic is comprised of eight shared latches. only one side can control the latch (semaphor e) at any time. control of a semaphore indicates that a shared resource is in use. an automatic power-down feature is controlled independently on each port by a chip select (ce ) pin. the cy7c009v is available in 100-pin thin quad plastic flatpacks (tqfp).
cy7c009v document number: 38-06044 rev. *g page 3 of 23 contents selection guide ................................................................ 4 pin configurations ........................................................... 4 pin definitions .................................................................. 5 architecture ...................................................................... 5 functional overview ........................................................ 5 write operation ........................................................... 5 read operation ........................................................... 5 interrupts ..................................................................... 5 busy ............................................................................ 5 master/slave ............................................................... 5 semaphore operation ............ .............. .............. ......... 6 maximum ratings ............................................................. 8 operating range ............................................................... 8 electrical characteristics ................................................. 8 capacitance ...................................................................... 9 ac test loads and waveforms ....................................... 9 data retention mode ........................................................ 9 timing ................................................................................ 9 switching characteristics .............................................. 10 switching waveforms .................................................... 12 ordering information ...................................................... 18 128 k 8, 3.3 v asynchronous dual-port sram ..... 18 ordering code definitions ..... .................................... 18 package diagram ............................................................ 19 acronyms ........................................................................ 20 document conventions ................................................. 20 units of measure ....................................................... 20 document history page ................................................. 21 sales, solutions, and legal information ...................... 23 worldwide sales and design s upport ......... .............. 23 products .................................................................... 23 psoc? solutions ...................................................... 23 cypress developer community ................................. 23 technical support ................. .................................... 23
cy7c009v document number: 38-06044 rev. *g page 4 of 23 selection guide description cy7c009v ?15 cy7c009v ?20 cy7c009v ?25 unit maximum access time 15 20 25 ns typical operating current 125 120 115 ma typical standby current for i sb1 (both ports ttl level) 35 35 30 ma typical standby current for i sb3 (both ports cmos level) 10 10 10 ? a pin configurations figure 1. 100-pin tqfp pinout (top view) 1 3 2 92 91 90 84 85 87 86 88 89 83 82 81 76 78 77 79 80 93 94 95 96 97 98 99 100 59 60 61 67 66 64 65 63 62 68 69 70 75 73 74 72 71 nc nc a7r a8r a9r a10r a15r a12r a14r gnd nc nc ce 0r a13r a11r nc nc ce1r sem r r/w r oe r gnd gnd nc a16r 58 57 56 55 54 53 52 51 nc nc a7l a8l a9l a10l a15l a12l a14l vcc nc nc ce 0l a13l a11l nc nc ce1l sem l r/w l oe l gnd nc nc a16l 17 16 15 9 10 12 11 13 14 8 7 6 4 5 18 19 20 21 22 23 24 25 nc nc a6l a5l a4l a3l int l a1l nc gnd m/s a0r a1r a0l a2l busy r int r a2r a3r a4r a5r a6r nc nc busy l 34 35 36 42 41 39 40 38 37 43 44 45 50 48 49 47 46 nc nc nc i/o7r i/o6r i/o5r i/01r i/o3r i/o2r gnd vcc gnd i/o2l vcc i/o4r i/o0l i/o1l i/o3l i/o4l i/o5l i/o6l i/o7l nc gnd i/o0r 33 32 31 30 29 28 27 26 cy7c009v (128 k 8)
cy7c009v document number: 38-06044 rev. *g page 5 of 23 architecture the cy7c009v consists of an arra y of 128 k words of 8 bits each of dual-port ram cells, i/o and address lines, and control signals (ce , oe , r/w ). these control pins permit independent access for reads or writes to any location in memory. to handle simultaneous writes/reads to the same location, a busy pin is provided on each port. two interrupt (int ) pins can be utilized for port-to-port communication. two semaphore (sem ) control pins are used for allocating shared resources. with the m/s pin, the devices can function as a master (busy pins are outputs) or as a slave (busy pins are inputs). the devices also have an automatic power-down feature controlled by ce . each port is provided with its own output enable control (oe ), which allows data to be read from the device. functional overview write operation data must be set up for a duration of t sd before the rising edge of r/w in order to guarantee a vali d write. a writ e operation is controlled by either the r/w pin (see write cycle no. 1 waveform) or the ce pin (see write cycle no. 2 waveform). required inputs for non-contention operations are summarized in table 1 on page 6 . if a location is being written to by one port and the opposite port attempts to read that location, a port-to-port flowthrough delay must occur before the data is r ead on the output; otherwise the data read is not deterministic. data will be valid on the port t ddd after the data is presented on the other port. read operation when reading the device, the user must assert both the oe and ce pins. data will be available t ace after ce or t doe after oe is asserted. if the user wishes to access a semaphore flag, then the sem pin must be asserted instead of the ce pin, and oe must also be asserted. interrupts the upper two memory locations may be used for message passing. the highest memory location (1ffff for the cy7c009) is the mailbox for the right port and the second-highest memory location (1fffe for the cy7c009) is the mailbox for the left port. when one port writes to the other port?s mailbox, an interrupt is generated to the owner. the interrupt is reset when the owner reads the contents of the mailbox. the message is user defined. each port can read the other port?s mailbox without resetting the interrupt. the active state of the busy signal (to a port) prevents the port from setting the interrupt to the winning port. also, an active busy to a port prevents that port from reading its own mailbox and, thus, resetting the interrupt to it. if an application does not require message passing, do not connect the interrupt pin to the processor?s interrupt request input pin. the operation of the interrupts and their interaction with busy are summarized in table 2 on page 6 . busy the cy7c009v provide on-chip arbitration to resolve simultaneous memory location access (contention). if both ports? ce s are asserted and an address match occurs within t ps of each other, the busy logic will determine which port has access. if t ps is violated, one port will definitely gain permission to the location, but it is not predictable which port will get that permission. busy will be asserted t bla after an address match or t blc after ce is taken low. master/slave a m/s pin is provided in order to expand the word width by configuring the device as either a master or a slave. the busy output of the master is connected to the busy input of the slave. this will allow the device to interface to a master device with no external components. writing to slave devices must be delayed until after the busy input has settled (t blc or t bla ), otherwise, pin definitions left port right port description ce 0l , ce 1l ce 0r , ce 1r chip enable (ce is low when ce 0 ??? v il and ce 1 ? v ih ) r/w l r/w r read/write enable oe l oe r output enable a 0l ?a 16l a 0r ?a 16r address i/o 0l ?i/o 7l i/o 0r ?i/o 7r data bus input/output sem l sem r semaphore enable int l int r interrupt flag busy l busy r busy flag m/s master or slave select v cc power gnd ground nc no connect
cy7c009v document number: 38-06044 rev. *g page 6 of 23 the slave chip may begin a write cycle during a contention situation. when tied high, the m/s pin allows the device to be used as a master and, therefore, the busy line is an output. busy can then be used to send the arbitration outcome to a slave. semaphore operation the cy7c009v provide eight semaphore latches, which are separate from the dual-port memory locations. semaphores are used to reserve resources that are shared between the two ports.the state of the semaphore indicates that a resource is in use. for example, if the left port wants to request a given resource, it sets a latch by writing a zero to a semaphore location. the left port then verifies its success in setting the latch by reading it. after writing to the semaphore, sem or oe must be deasserted for t sop before attempting to read the semaphore. the semaphore value will be available t swrd + t doe after the rising edge of the semaphore write. if the left port was successful (reads a zero), it assumes cont rol of the shared resource, otherwise (reads a one) it assumes the right port has control and continues to poll the semaphore. when the right side has relinquished control of the semaphore (by writing a one), the left side will succeed in gaining control of the semaphore. if the left side no longer requires the semaph ore, a one is written to cancel its request. semaphores are accessed by asserting sem low. the sem pin functions as a chip select for the semaphore latches (ce must remain high during sem low). a 0?2 represents the semaphore address. oe and r/w are used in the same manner as a normal memory access. when writing or reading a semaphore, the other addre ss pins have no effect. when writing to the semaphore, only i/o 0 is used. if a zero is written to the left port of an available semaphore, a one will appear at the same semaphore address on the right port. that semaphore can now only be modified by the side showing zero (the left port in this case). if the left port now relinquishes control by writing a one to the semaphore, the semaphore will be set to one for both sides. however, if the right port had requested the semaphore (written a zero) while the left port had control, the right port would immediately own the semaphore as soon as the left port released it. table 3 on page 7 shows sample semaphore operations. when reading a semaphore, all da ta lines output the semaphore value. the read value is latched in an output register to prevent the semaphore from changing state during a write from the other port. if both ports attempt to access the semaphore within t sps of each other, the semaphore will definitely be obtained by one side or the other, but there is no guarantee which side will control the semaphore. table 1. non-contending read/write inputs outputs operation ce r/w oe sem i/o 0 ? i/o 8 h x x h high z deselected: power-down h h l l data out read data in semaphore flag x x h x high z i/o lines disabled h x l data in write into semaphore flag l h l h data out read l l x h data in write l x x l not allowed table 2. interrupt operation example (assumes busy l = busy r = high) function left port right port r/w l ce l oe l a 0l?16l int l r/w r ce r oe r a 0r?16r int r set right int r flag l l x 1ffff x x x x x l [2] reset right int r flag x x x x x x l l 1ffff h [3] set left int l flag xxx x l [3] l l x 1fffe x reset left int l flag x l l 1fffe h [2] xxxxx notes 2. if busy l = l, then no change. 3. if busy r = l, then no change.
cy7c009v document number: 38-06044 rev. *g page 7 of 23 table 3. semaphore operation example function i/o 0 ? i/o 8 left i/o 0 ? i/o 8 right status no action 1 1 semaphore free left port writes 0 to semaphore 0 1 left port has semaphore token right port writes 0 to semaphore 0 1 no change. right side has no write access to semaphore left port writes 1 to semaphore 1 0 right port obtains semaphore token left port writes 0 to semaphore 1 0 no change. left port has no write access to semaphore right port writes 1 to semaphore 0 1 left port obtains semaphore token left port writes 1 to semaphore 1 1 semaphore free right port writes 0 to semaphore 1 0 right port has semaphore token right port writes 1 to semaphore 1 1 semaphore free left port writes 0 to semaphore 0 1 left port has semaphore token left port writes 1 to semaphore 1 1 semaphore free
cy7c009v document number: 38-06044 rev. *g page 8 of 23 maximum ratings exceeding maximum ratings [4] may shorten the useful life of the device. user guidelines are not tested. storage temperature .. ............... ............... ?65 c to +150 c ambient temperature with power applied .......................................... ?55 ? c to +125 ? c supply voltage to ground potential ..............?0.5 v to +4.6 v dc voltage applied to outputs in high z state ........................ ?0.5 v to v cc + 0.5 v dc input voltage ................................. ?0.5 v to v cc + 0.5 v output current into outputs (low) ............................. 20 ma static discharge voltage ......................................... > 1100 v latch-up current ................................................... > 200 ma operating range range ambient temperature v cc commercial 0 c to +70 c 3.3 v 300 mv industrial [5] ?40 c to +85 c 3.3 v 300 mv electrical characteristics over the operating range parameter description cy7c009v unit -15 -20 -25 min typ max min typ max min typ max v oh output high voltage (v cc = min, i oh = ?4.0 ma) 2.4 ? ? 2.4 ? ? 2.4 ? ? v v ol output low voltage (v cc = min, i oh = +4.0 ma) ? 0.4 ? 0.4 ? 0.4 v v ih input high voltage 2.2 ? 2.2 ? 2.2 ? v v il input low voltage ? 0.8 ? 0.8 ? 0.8 v i ix input leakage current ?5 5 ?5 5 ?5 5 ? a i oz output leakage current ?10 10 ?10 10 ?10 10 ? a i cc operating current (v cc = max, i out = 0 ma) outputs disabled commercial ? 125 185 ? 120 175 ? 115 165 ma industrial ? 140 195 ? ma i sb1 standby current (both ports ttl level) ce l and ce r ? v ih , f = f max commercial 35 50 35 45 30 40 ma industrial ? 45 55 ? ma i sb2 standby current (one port ttl level) ce l | ce r ? v ih , f = f max commercial 80 120 75 110 65 95 ma industrial ? 85 120 ? ma i sb3 standby current (both ports cmos level) ce l and ce r ? v cc ?? 0.2 v, f = 0 commercial 10 250 10 250 10 250 ? a industrial ? 10 250 ? ? a i sb4 standby current (one port cmos level) ce l | ce r ? v ih , f = f max [6] commercial 75 105 70 95 60 80 ma industrial ? 80 105 ? ma notes 4. the voltage on any input or i/o pin cannot exceed the power pin during power-up. 5. industrial parts are available in cy7c009v. 6. f max = 1/t rc = all inputs cycling at f = 1/t rc (except output enable). f = 0 means no address or control li nes change. this applies only to inputs at cmos level standby i sb3 .
cy7c009v document number: 38-06044 rev. *g page 9 of 23 data retention mode the cy7c009v is designed with battery backup in mind. data retention voltage and supply current are guaranteed over temperature. the following rules ensure data retention: 1. chip enable (ce ) must be held high during data retention, within v cc to v cc ? 0.2 v. 2. ce must be kept between v cc ? 0.2 v and 70% of v cc during the power-up and power-down transitions. 3. the ram can begin operation > t rc after v cc reaches the minimum operating voltage (3.0 v). capacitance parameter [7] description test conditions max unit c in input capacitance t a = 25 c, f = 1 mhz, v cc = 3.3 v 10 pf c out output capacitance 10 pf ac test loads and waveforms figure 2. ac test loads and waveforms 3.0 v gnd 90% 90% 10% 3ns 3 ns 10% all input pulses (a) normal load (load 1) r1 = 590 ? 3.3 v output r2 = 435 ? c = 30 pf v th = 1.4 v output (b) thvenin equivalent (load 1) (c) three-state delay (load 2) 3.3 v output r th = 250 ? ? ? including scope and jig) (used for t lz , t hz , t hzwe, & t lzwe c = 30 pf c = 5 pf r1 = 590 ? r2 = 435 ? [8] max unit icc dr1 @ vcc dr = 2 v 50 ? a data retention mode 3.0 v 3.0 v v cc ? ? 2.0 v v cc to v cc ? 0.2 v v cc ce t rc v ih notes 7. tested initially and after any design or proces s changes that may affect these parameters. 8. ce = v cc , v in = gnd to v cc , t a = 25 ?? c. this parameter is guaranteed but not tested.
cy7c009v document number: 38-06044 rev. *g page 10 of 23 switching characteristics over the operating range parameter [9] description cy7c009v unit -15 -20 -25 min max min max min max read cycle t rc read cycle time 15?20?25?ns t aa address to data valid ? 15 ? 20 ? 25 ns t oha output hold from address change 3?3?3?ns t ace [10] ce low to data valid ? 15 ? 20 ? 25 ns t doe oe low to data valid ? 10 ? 12 ? 13 ns t lzoe [11, 12, 13] oe low to low z 3?3?3?ns t hzoe [11, 12, 13] oe high to high z ? 10 ? 12 ? 15 ns t lzce [11, 12, 13] ce low to low z 3?3?3?ns t hzce [11, 12, 13] ce high to high z ?10?12?15ns t pu [13] ce low to power-up 0?0?0?ns t pd [13] ce high to power-down ?15?20?25ns t abe [10] byte enable access time ? 15 ? 20 ? 25 ns write cycle t wc write cycle time 15 ? 20 ? 25 ? ns t sce [10] ce low to write end 12 ? 16 ? 20 ? ns t aw address valid to write end 12 ? 16 ? 20 ? ns t ha address hold from write end 0?0?0?ns t sa [10] address set-up to write start 0?0?0?ns t pwe write pulse width 12 ? 17 ? 22 ? ns t sd data set-up to write end 10 ? 12 ? 15 ? ns t hd data hold from write end 0?0?0?ns t hzwe [12, 13] r/w low to high z ? 10 ? 12 ? 15 ns t lzwe [12, 13] r/w high to low z 3?3?3?ns t wdd [14] write pulse to data delay ? 30 ? 40 ? 50 ns t ddd [14] write data valid to read data valid ? 25 ? 30 ? 35 ns notes 9. test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5 v, input pulse levels of 0 to 3 .0 v, and output loading of the specified i oi /i oh and 30 pf load capacitance. 10. to access ram, ce = l, sem = h. to access semaphore, ce = h and sem = l. either condition must be valid for the entire t sce time. 11. at any given temperature and voltage condition for any given device, t hzce is less than t lzce and t hzoe is less than t lzoe . 12. test conditions used are load 2. 13. this parameter is guaranteed by design, but it is not production tested.for information on port-to-port delay through ram ce lls from writing port to reading port, refer to read timing with busy waveform. 14. for information on port-to-port delay through ram cells from writing port to reading port, refer to read timing with busy wa veform.
cy7c009v document number: 38-06044 rev. *g page 11 of 23 busy timing [15] t bla busy low from address match ? 15 ? 20 ? 20 ns t bha busy high from address mismatch ? 15 ? 20 ? 20 ns t blc busy low from ce low ?15?20?20ns t bhc busy high from ce high ?15?16?17ns t ps port set-up for priority 5?5?5?ns t wb r/w high after busy (slave) 0?0?0?ns t wh r/w high after busy high (slave)13?15?17?ns t bdd [16] busy high to data valid ?15?20?25ns interrupt timing [15] t ins int set time ? 15 ? 20 ? 20 ns t inr int reset time ?15?20?20ns semaphore timing t sop sem flag update pulse (oe or sem )10?10?12?ns t swrd sem flag write to read time 5?5?5?ns t sps sem flag contention window 5 ? 5?5?ns t saa sem address access time ? 15 ? 20 ? 25 ns switching characteristics (continued) over the operating range parameter [9] description cy7c009v unit -15 -20 -25 min max min max min max notes 15. test conditions used are load 1. 16. t bdd is a calculated parameter and is the greater of t wdd ?t pwe (actual) or t ddd ?t sd (actual).
cy7c009v document number: 38-06044 rev. *g page 12 of 23 switching waveforms figure 3. read cycle no.1 (either port address access) [17, 18, 19] figure 4. read cycle no.2 (either port ce /oe access) [17, 20, 21] figure 5. read cycle no. 3 (either port) [17, 19, 20, 21] t rc t aa t oha data valid previous data valid data out address t oha t ace t lzoe t doe t hzoe t hzce data valid t lzce t pu t pd i sb i cc data out oe ce current data out t rc address t aa t oha ce t lzce t abe t hzce t ace t lzce notes 17. r/w is high for read cycles. 18. device is continuously selected ce = v il . this waveform cannot be used for semaphore reads. 19. oe = v il . 20. address valid prior to or coincident with ce transition low. 21. to access ram, ce = v il , sem = v ih . to access semaphore, ce = v ih , sem = v il .
cy7c009v document number: 38-06044 rev. *g page 13 of 23 figure 6. write cycle no. 1: r/w controlled timing [22, 23, 24, 25] figure 7. write cycle no. 2: ce controlled timing [22, 23, 24, 29] switching waveforms (continued) t aw t wc t pwe t hd t sd t ha ce r/w oe data out data in address t hzoe t sa t hzwe t lzwe [26] [26] [25] [27] note 28 note 28 t aw t wc t sce t hd t sd t ha ce r/w data in address t sa [27] notes 22. r/w must be high during all address transitions. 23. a write occurs during the overlap (t sce or t pwe ) of a low ce or sem . 24. t ha is measured from the earlier of ce or r/w or (sem or r/w ) going high at the end of write cycle. 25. if oe is low during a r/w controlled write cycle, the write pulse width must be the larger of t pwe or (t hzwe + t sd ) to allow the i/o drivers to turn off and data to be placed on the bus for the required t sd . if oe is high during an r/w controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified t pwe . 26. transition is measured ? 500 mv from steady state with a 5 pf load (including sc ope and jig). this parameter is sampled and not 100% tested. 27. to access ram, ce = v il , sem = v ih . 28. during this period, the i/o pins are in the output state, and input signals must not be applied. 29. if the ce or sem low transition occurs simultaneously with or after the r/w low transition, the outputs remain in the high-impedance state.
cy7c009v document number: 38-06044 rev. *g page 14 of 23 figure 8. semaphore read after write timing, either side [30] figure 9. timing diagra m of semaphore contention [31, 32, 33] switching waveforms (continued) t sop t saa valid adress valid adress t hd data in valid data out valid t oha t aw t ha t ace t sop t sce t sd t sa t pwe t swrd t doe write cycle read cycle oe r/w i/o 0 sem a 0 ?a 2 match t sps a 0l ?a 2l match r/w l sem l r/w r sem r a 0r ?a 2r notes 30. ce = high for the duration of the above timing (both write and read cycle). 31. i/o 0r = i/o 0l = low (request semaphore); ce r = ce l = high. 32. semaphores are reset (availabl e to both ports) at cycle start. 33. if t sps is violated, the semaphore will definitely be obtained by one si de or the other, but which side will get the semaphore is unpr edictable.
cy7c009v document number: 38-06044 rev. *g page 15 of 23 figure 10. timing diagram of read with busy (m/s = high) [34] figure 11. write timing with busy input (m/s = low) switching waveforms (continued) valid t ddd t wdd match match r/w r data in r data outl t wc address r t pwe valid t sd t hd address l t ps t bla t bha t bdd busy l t pwe r/w busy t wb t wh note 34. ce l = ce r = low.
cy7c009v document number: 38-06044 rev. *g page 16 of 23 figure 12. busy timing diagram no. 1 (ce arbitration) [35] figure 13. busy timing diagram no. 2 (address arbitration) [35] switching waveforms (continued) address match t ps t blc t bhc address match t ps t blc t bhc address l,r busy r ce l ce r busy l ce r ce l address l,r ce l valid first: ce r valid first: address match t ps address l busy r address mismatch t rc or t wc t bla t bha address r address match address mismatch t ps address l busy l t rc or t wc t bla t bha address r right address valid first: left address valid first: note 35. if t ps is violated, the busy signal will be asserted on one side or the other, but there is no guarantee to which side busy will be asserted.
cy7c009v document number: 38-06044 rev. *g page 17 of 23 figure 14. interru pt timing diagrams switching waveforms (continued) write 1ffff t wc t ha read 1ffff t rc t inr write 1fffe t wc read 1fffe t inr t rc address r ce l r/w l int l oe l address r r/w r ce r int l address r ce r r/w r int r oe r address l r/w l ce l int r t ins t ha t ins [36] [37] [37] [37] [36] [37] left side clears int l : right side sets int l : right side clears int r : left side sets int r : notes 36. t ha depends on which enable pin (ce l or r/w l ) is deasserted first. 37. t ins or t inr depends on which enable pin (ce l or r/w l ) is asserted last.
cy7c009v document number: 38-06044 rev. *g page 18 of 23 ordering information ordering code definitions 128 k 8, 3.3 v asynchronous dual-port sram speed (ns) ordering code package name package type operating range 15 CY7C009V-15AXC a100 100-pin tqfp pb-free commercial 20 cy7c009v-20axi a100 100-pin tqfp pb-free industrial 25 cy7c009v-25axc a100 100-pin tqfp pb-free commercial operating range: x = c or i c = commercial; i = industrial pb-free package: a = 100-pin tqfp speed bin: xx = 15 or 20 or 25 3.3 v part 64 k / 128 k dual port family 00 = 8 technology code: c = cmos marketing code: 7 = sram company id: cy = cypress 7 cy 00 v - xx a c 9 x x
cy7c009v document number: 38-06044 rev. *g page 19 of 23 package diagram figure 15. 100-pin tqfp (14 14 1. 4 mm) a100sa package outline, 51-85048 51-85048 *h
cy7c009v document number: 38-06044 rev. *g page 20 of 23 acronyms document conventions units of measure acronym description cmos complementary metal oxide semiconductor ce chip enable i/o input/output int interrupt oe output enable sem semaphore sram static random access memory tqfp thin quad flat pack ttl transistor-transistor logic symbol unit of measure c degree celsius mhz megahertz a microampere ma milliampere ms millisecond mv millivolt ns nanosecond pf picofarad vvolt wwatt
cy7c009v document number: 38-06044 rev. *g page 21 of 23 document history page document title: cy7c009v, 3.3 v 128 k 8 dual-port static ram document number: 38-06044 rev. ecn no. issue date orig. of change description of change ** 110192 09/29/01 szv change from spec number: 38-00669 to 38-06044 *a 113541 04/15/02 oor updated pin configurations (changed pin 85 from busy l to busy r in the figure ?100-pin tqfp (top view)? (corresponding to cy7c018v/019v)). *b 122294 12/27/02 rbi updated maximum ratings (added power up requirements). *c 393440 see ecn yim added pb-free logo updated ordering information (added pb-free parts (cy7c008v-25axc, CY7C009V-15AXC, cy7c009v-20axi, cy7c009v-25axc, cy7c019v-15axc, cy7c019v-20axc, cy7c019v-20axi, cy7c019v-25axc)). *d 2896038 03/19/10 rame updated ordering information (removed inactive parts). updated package diagram . *e 3081242 11/09/2010 admu added ordering code definitions . added acronyms and units of measure . minor edits and updated in new template. *f 3816114 11/19/2012 smch updated document title to read ?cy7c009v, 3.3 v 128 k 8 dual-port static ram?. updated features (removed cy7c008v, cy7c018v, cy7c019v related information). updated logic block diagram (removed cy7c008v, cy7c018v, cy7c019v related information, removed notes ?i/o 0 ?i/o 7 for 8 devices; i/o 0 ?i/o 8 for 9 devices.? and ?a 0 ?a 15 for 64 k devices; a 0 ?a 16 for 128 k.? and their references in logic block diagram). updated functional description (removed cy7c008v, cy7c018v, cy7c019v related information). updated selection guide (removed cy7c008v, cy7c018v, cy7c019v related information). updated pin configurations (updated figure 1 (removed cy7c008v related information, removed the note ?this pin is nc for cy7c008v.? and its reference in the same figure), removed the figure ?100-pin tqfp (top view)?, removed the note ?this pin is nc for cy7c018v.?). updated pin definitions (removed cy7c008v, cy7c018v, cy7c019v related information). updated architecture (removed cy7c008v, cy7c018v, cy7c019v related information). updated functional overview (updated interrupts (removed cy7c008v, cy7c018v, cy7c019v related information), updated busy (removed cy7c008v, cy7c018v, cy7c019v related information), updated semaphore operation (removed cy7c008v, cy7c018v, cy7c019v related information), updated table 2 (removed cy7c008v, cy7c018v, cy7c019v related information), remo ved the note ?a 0l?16l and a 0r?16r , 1ffff/1fffe for the cy7c009v/19v.? and its reference in the same table)). updated operating range (updated note 5 (removed cy7c019v related information)). updated electrical characteristics (removed cy7c008v, cy7c018v, cy7c019v related information, removed the note ?industrial parts are available in cy7c009v and cy7c019v only.? and its reference in electrical characteristics). updated data retention mode (removed cy7c008v, cy7c018v, cy7c019v related information). updated switching characteristics (removed cy7c008v, cy7c018v, cy7c019v related information, updated note 10 (removed ub = l)).
cy7c009v document number: 38-06044 rev. *g page 22 of 23 *f (cont.) 3816114 11/19/2012 smch updated switching waveforms (updated figure 14 (removed cy7c019v related info rmation)). updated package diagram (spec 51-85048 (changed revision from *d to *g)). *g 4194765 11/18/2013 smch updated pin definitions : replaced ?ce r , ce 1r ? with ?ce 0r , ce 1r ? in ?right port? column. updated switching waveforms : updated figure 14 . updated package diagram : spec 51-85048 ? changed revision from *g to *h. updated in new template. completing sunset review. document history page (continued) document title: cy7c009v, 3.3 v 128 k 8 dual-port static ram document number: 38-06044 rev. ecn no. issue date orig. of change description of change
document number: 38-06044 rev. *g revised november 18, 2013 page 23 of 23 all products and company names mentioned in this document may be the trademarks of their respective holders. cy7c009v ? cypress semiconductor corporation, 2001-2013. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement wi th cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representatives, and distributors. to find t he office closest to you, visit us at cypress locations . products automotive cypress.co m/go/automotive clocks & buffers cypress.com/go/clocks interface cypress. com/go/interface lighting & power control cypress.com/go/powerpsoc cypress.com/go/plc memory cypress.com/go/memory psoc cypress.com/go/psoc touch sensing cyp ress.com/go/touch usb controllers cypress.com/go/usb wireless/rf cypress.com/go/wireless psoc ? solutions psoc.cypress.com/solutions psoc 1 | psoc 3 | psoc 4 | psoc 5lp cypress developer community community | forums | blogs | video | training technical support cypress.com/go/support

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